The present invention relates to a semiconductor memory device which can execute an operating test at a high speed.
This application is related to the commonly assigned copening application of Ohta entitled "Semiconductor Memory Device", filed Nov. 14, 1990 and assigned Ser. No. 07/612,503 pending.
Recent advances in semiconductor memory devices have been rapid, with the degree of integration of random access memories (RAMs), read-only memories (ROMs), and other memory devices quadrupling every three years. As the degree of integration has increased, the time required to execute an operating test has also increased, thus increasing the need for a high speed test mode enabling more efficient pre-shipment testing by the manufacturer and receival testing by the user.
Reflecting these requirements, a test method called a multi-bit test method has been used. This method reads test data from two memory cells at a time and compares data read from one memory cell with that read from the other memory cell. When the data read from both memory cells are coincident, data reading is regarded as normally executed. This method realizes a speedy test, as compared with a method by which data is read from each one of the memory cells and checked. Still, it cannot be said that the multi-bit test method satisfies the above requirements. In addition, if the data reading from two memory cells are both in error, those data become coincident and therefore misjudged as normally read.